HARDWARE MODELLING USING VERILOG, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

The Department of Electrical and Electronics Engineering, KPR Institute of Engineering and Technology, Coimbatore, organized an Expert Lecture on “Hardware Modelling Using Verilog” on 07 October 2026 (Wednesday) from 2.00 p.m. to 4.00 p.m. at the II EEE Classroom. The session was delivered by Dr. I. Baranilingesan, Assistant Professor-III/EEE, KPRIET.

The expert lecture was organized to strengthen students’ understanding of hardware description and digital circuit modelling using Verilog HDL. The session introduced the significance of Hardware Description Languages in the design, simulation, and verification of digital systems. The resource person explained the basic structure of Verilog programs, modules, data types, operators, and different modelling approaches such as gate-level, dataflow, and behavioural modelling.

During the session, students were exposed to the modelling of combinational and sequential digital circuits using Verilog. The lecture also highlighted the importance of writing effective test benches, performing simulation, verifying the functionality of digital designs, and understanding the role of Verilog in FPGA and VLSI-based system development. Relevant examples were discussed to connect theoretical concepts with practical digital hardware implementation.

The session was interactive and provided students with an opportunity to clarify their doubts regarding Verilog coding, simulation, and hardware realization. The expert lecture enhanced the students’ practical understanding of digital system design and motivated them to explore advanced applications of Verilog in embedded systems, FPGA design, and VLSI technologies.

Outcome

At the end of the session, the students were able to understand the fundamentals of Verilog HDL, distinguish different hardware modelling styles, develop Verilog descriptions for basic digital circuits, and appreciate the process of simulation and functional verification. The programme strengthened their skills in hardware modelling and provided a foundation for further learning in FPGA, VLSI, and digital system design.