The entire technical training content are Power estimation, Speed estimation, Area optimization and delay estimation of various combinational circuits. And also discussed about estimation of resistance, load capacitance, parasitic delay of CMOS circuits. It uses pre-designed logic cell(and gates, OR gate, multiplexers) known as standard cells. Designer used pre-tested or pre-characterized cell. Design time and complexity is less
KPRIET – An AI Integrated Campus
Preparing future-ready engineers with AI-integrated teaching and learning. KPRIET integrates Artificial Intelligence across teaching, learning, research and innovation to create a smarter, future-ready campus experience for students and faculty.
